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LAYTOOLS from Catena, Netherlands

LAYTOOLS are especially developed for electronic layout design. With its powerful multi-window all-angle IC layout editor, the drawing of IC layouts is easy and quickly mastered, even in the case of very complex structures. LAYTOOLS is available for PC-Windows, LINUX & UNIX. Furthermore our programme contains circuit and power-electronics simulators.

SPE : The Schematic Editor

SPE is a schematic capture package available for MS-Windows platforms and offers designers a more complete choice in affordable design solutions.


Schematic graphical data may be created and processed in a hierarchically structured form.

Data comprise of symbols, schematic elements, attributes, text, buses, bus taps, pins and wires (nets) connecting the used components.

Symbols are the basic elements of a schematic and represent primitive devices (resistors, gates, etc.) or complex sub-circuits ("BLOCK" Symbols.)

Attributes describe characteristics or properties of associated symbols, pins, or nets.

Symbol files are usually contained in library directories used for several schematics.

SPE includes a NETLISTER for the output of netlist files in several formats as XNDL, SPICE, SMASH, SDL, VHDL, HILO, and EDIF used for layout generation (place/route tools like LAYPAR), for layout verification (e.g. LAYVER), or for Simulation (e.g PSpice).

Crossprobing can be carried out together with the tool LAYED when editing in SDLE mode or viewing LAYVER evaluation results.

Schematic consistency checks can be carried out.

Back annotation for simulation results. Current version supports SMASH.

LAYED : Layout Editor

LAYED was especially developed for electronic layout design.
With the extensive LAYED command set, the drawing of IC layouts is easy and quickly mastered, even in the case of very complex structures. These commands are available in pull-down menus, through optional icons (the tool box) and under short-cut keys. Direct entry of the commands via the keyboard is supported as well.

Advanced Edit Features

Hierarchical data structures

Evaluation of LAYVER results

LAYVER: Layout Verification

The Layout Verification System LAYVER provides the user with tools to:
Check an IC layout design with respect to technological design rules (DRC).
Extract the realized (on chip) circuit and compare it with the desired circuit (LVS).
Derive new layers by shrinking or bloating a layer or perform logical operations on layers.
Calculate physical and electrical parameters that depend on the geometry of drawn regions and set minimum and maximum check limits to these parameters for the LVS.

Design Rule Check (DRC)

Full flexibility of circuit extraction - no fixed technologies

Output facilities

LAYPAR: Place and Route

LAYPAR is a program for automatic creation of standard cell arrays. LAYPAR comprises the two main components LAYPLACE and LAYROUTE as well as a dialog frame and additional conversion tools.

LAYPLACE : Cell Placement

Features: Generation of feed cell instances dependent on a given quota and deviation mirroring of cells and cell rows working with user-controlled effort in pre-, coarse and fine placement.

LAYROUTE : Auto Routing

Features: Global routing based on a user-defined grid feed through handling and over cell routing 3-layer channel routing generation of cell block layout in all supported layout formats consideration of locked regions by the routing process.
LAYPLOT: Layout Plot Program
LAYDRAC: Conversion Tool to LAYVER
LAYCON: Conversion Tool CIF
LAYGERB: Conversion Tool GERBER
DBXMAN: Database Library Manager


Catena Holding BV
40 2628 XG Delft
The Netherlands
Tel: +31 15 275 6000
Fax: +31 15 275 6060
Web :

201/202, C-2, Saudamani Commercial Complex,
Bhusari Colony, Paud Road, Kothrud, Pune - 411 038
Maharashtra, India 
Contact no.: +91 20 2528 6947 / 8